1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having an interconnection pattern formed on a semiconductor substrate using a photolithography method.
2. Description of the Background Art
A photolithography method is conventionally known as a method of forming an interconnection pattern to which the gate electrode and the like of a transistor formed on a semiconductor substrate are connected. FIG. 1 is a plan layout diagram of a semiconductor device having an interconnection pattern to which the gate electrode of a conventional transistor is connected. FIG. 2 is a perspective view of a conventional semiconductor device shown in FIG. 1.
Referring to FIGS. 1 and 2, a semiconductor device having a conventional interconnection pattern is provided with a semiconductor silicon substrate 101, an element isolation film (an LOCOS film) 102 formed in a predetermined region on the main surface of semiconductor silicon substrate 101 for isolating elements, a pair of interconnection patterns 131 and 132 formed to extend in a predetermined direction at a predetermined space on the surface of element isolation film 102, oxide films (SiO.sub.2 films) 133 and 134 formed to cover interconnection patterns 131 and 132 and each having an opening in the center of the top surface of interconnection patterns 131 and 132, a gate electrode 108a formed to cover a predetermined region on an active region 110a surrounded by element isolation film 102 and interconnection pattern 131, and a gate electrode 108b formed to cover a predetermined region on an active region 110b and interconnection pattern 132. Gate electrode 108a and interconnection pattern 131 are electrically connected through a contact hole of oxide film 133. Gate electrode 108b and interconnection pattern 132 are electrically connected through a contact hole of oxide film 134.
FIGS. 3 to 9 show cross-sectional views for explaining a manufacturing process (the first step to the seventh step) of a conventional semiconductor device shown in FIG. 2. Referring to FIGS. 2 to 9, the manufacturing process of a conventional semiconductor device will now be described.
First, as shown in FIG. 3, isolation oxide film 102 is formed in a predetermined region on semiconductor silicon substrate 101 using an LOCOS method. A polysilicon layer 130, which is an interconnection material, is formed on the whole surface of the film.
Next, as shown in FIG. 4, organic resists 140 are formed in a predetermined region on polysilicon layer 130 using a photolithography method. Polysilicon layer 130 is anisotropically etched with organic resists 140 used as mask.
As shown in FIG. 5, a pair of interconnection patterns 131, 132 having a predetermined space therebetween are formed.
Next, as shown in FIG. 6, oxide films (SiO.sub.2 films) 133a and 134a are formed to cover interconnection patterns 131 and 132, respectively. Organic resists 150 are formed on a region excluding the centers of the top surfaces of interconnection patterns 131 and 132. Oxide films 133a and 134a positioned on the centers of the top surfaces of interconnection patterns 131 and 132, respectively, are removed by carrying out anisotropical etching with organic resists 150 used as mask.
As shown in FIG. 7, oxide films 133 and 134 are formed which have an opening on the centers of top surfaces of interconnection patterns 131 and 132, respectively. A polysilicon layer 108 of a predetermined thickness is formed on the whole surface.
Next, as shown in FIG. 8, organic resists 160 are formed on a region having the gate electrode formed. The region is anisotropically etched with organic resists 160 used as mask.
As a result, as shown in FIG. 9, gate electrode 108a connected to interconnection pattern 131 and gate electrode 108b connected to interconnection pattern 132 are formed. In this way, a semiconductor device having an interconnection pattern to which the gate electrode and the like of a conventional transistor are connected is formed.
However, line width of interconnection patterns 131, 132 can only be miniaturized to be approximately the same as that of gate electrodes 108a, 108b in such a conventional manufacturing method of interconnection patterns 131, 132. More specifically, the minimum values of line width of gate electrodes 108a, 108b and line width of interconnection patterns 131, 132 are determined depending on the limit of processing in a photolithography technique. When semiconductor devices are more miniaturized as they are integrated in a larger scale, line width of gate electrodes 108a, 108b is miniaturized to the limit of processing in a photolithography method. Taking into consideration integration in a larger scale of interconnection patterns 131, 132, it is necessary to miniaturize the line width. However, it was not possible to have line width of interconnection patterns 131, 132 miniaturized to be less than the limit of processing in a photolithography method in a conventional method of forming interconnection patterns 131, 132. In other words, it was not possible to have line width of interconnection patterns 131, 132 miniaturized to be less than that of gate electrodes 108a, 108b. This has posed a problem in an attempt of integration of a semiconductor device (LSI) in a larger scale.